By attaching headers to all pins of the CPLD, MARC-2 is also easily expandable. A daughter board can be created by female connectors at the bottom and male headers at the top of a PCB. This way the signal lines are as short as possible. Talking about PCB and soldering, I have made this PCB at home but have to say that it’s my limit I'm willing to do at home. There are 720 pads and 168 vias so 888 holes to drill! The vias are hand soldered on the top and the back of the PCB with a very thin wire. Soldering all pads, vias and the expansion headers, I counted 1344 soldering joints.
I've used the following IC's:
- CPU WDC65C816S 16-bit processor @ 8MHz
- SRAM AS6C4008 512KiB RAM
- 'ROM' ATMega1284P (AVR) 16KiB ROM
- VIA0 WDC65C22S parallel port
- VIA1 WDC65C22S parallel port
- DUART SC26C92 2 serial ports
- RTC RV-3049-C2 real time clock
- CPLD XC95288XL TQ144 gluelogic, SPI, reset
- RS232 MAX232 RS323 level converter
Operation:
The AVR runs at 16MHz and provides that frequency to the CPLD at all times. The AVR senses the reset button and provides the overall reset signal to the CPLD. During RESET, the AVR copies the 16kB ROM image from its flash memory to the SRAM, which takes 79ms. After RESET the AVR becomes tri-stated, i.e. invisable to the system. This way there is no (E)EPROM needed. The SRAM can be easily expanded to 1MB by piggy backing an extra SRAM on top of it, the CS signal is already provided on a solder pad nearby.
The CLOCK is divided by 2 so that PHI2 is 8MHz. I'd hoped for this speed although I know it could probably be doubled. The 3.6864MHz for the DUART I also wanted to get from the CPLD, but instead of that, a quartz with two 22pF caps to ground takes care of it.
The CPU and SRAM are connected separately to the CPLD. This alone costs 51 I/O lines and some extra logic programming but gives the advantage of having VGA and DMA later on.
After various methods for providing a display for MARC-2:
I discovered the F18A FPGA based Video Display Processor.
The memory map looks like this:
RAM: $000000-$00BEFF
DUART: $00BF00-$00BF0F
VIA0: $00BF10-$00BF1F
VIA1: $00BF20-$00BF2F
F18A: $00BF80-$00BF81
SPI: $00BFF0-$00BFF3
RAM: $00C000-$07FFFF
I.e. there is RAM from $000000-$07FFFF except for the I/O page $00BF00-$00BFFF
Both VIA's are functional and free for use, however, nothing is connected to it right now.
The DUART is connected on channel A to a traditional RS232 port and channel B to a USB to TTL serial bridge. It's running by polling or interrupt based with 115200 baud without problems. I use TeraTerm to communicate with MARC-2.
The CPLD is configured with "Slow Output Slew Rate" and "Low Macrocell Power Setting". These settings reduce power consumption and noise. MARC-2 draws only 92mA from the USB port and there is almost no heat generated from the IC's. The MAX232 and the AVR get warm the most.
I have full control over MARC-2 by means of 3 USB devices:
• AVR DRAGON to update MARC-2's ROM image
• Xilinx USB cable to update the behavior of MARC-2
• USB to TTL serial to communicate with MARC-2 itself and
to provide 5V power
The development chain is extremely short and I use the following programs to update MARC-2's bios:
• TextPad with syntax highlighting (free text editor)
• ACME 65xxx cross assembler (free assembler for creating a 16kB rom.bin)
• bin2db.exe (C program which converts rom.bin to rom.inc)
• avrasm2.exe (ATMEL's assembler which assembles and includes rom.inc to the AVR firmware)
• atprogram.exe (ATMEL's programmer which flashes the AVR)
This whole cycle takes two mouse clicks and a few seconds to complete. It's also very convenient that the SBC will be reset after programming the AVR. Until I have a decent BIOS with file transfer and an external storage device, I'll continue using this method.
To program the CPLD I use ISE 10.1 SP3 which is freely available as a full version and is the last one which supports ABEL (and parallel programmer if preferred).
